As microelectronic processing techniques have improved, memory device capacities have increased. For example, dynamic random access memories include arrays of memory cells wherein each memory cell has a capacitor and a switching transistor to transmit information stored in the capacitor. As the size of a memory cell is reduced, more memory cells can be integrated into a single memory device thus increasing the capacity of that device. The performance of a memory cell with a relatively small storage capacitor, however, may be reduced due to increased soft error rates. Accordingly, the capacitance of a memory cell storage capacitor should be maintained at a sufficiently high level to provide adequate performance characteristics.
A memory cell capacitor includes a storage electrode, a dielectric layer, and a plate electrode. The capacitance of a storage capacitor can be increased by reducing the thickness of the dielectric layer, by increasing the effective area of the storage electrode, and by using dielectric materials having higher dielectric constants.
Three dimensional storage electrode structures have been developed to increase the capacitance of memory cell capacitors. For example, storage electrodes have been developed having planar structures, trench structures, stacked structures, and cylindrical structures as well as combinations of the aforementioned structures. These three dimensional electrode structures, however, may be difficult to fabricate using conventional processing techniques. Furthermore, these three dimensional structures may generate relatively large steps on the surface of the memory device. Memory cell capacitances have also been increased by using dielectric materials such as BST(BaSrTiO.sub.3) and PZT(PbZrTiO.sub.3) which have relatively ahigh dielectric constants. A method for forming capacitor structures including materials having high dielectric constants is illustrated in FIGS. 1A-1C.
In FIG. 1A, a conductive layer 3 is deposited on the substrate, a dielectric layer 5 is deposited on the conductive layer 3, and an alumina layer 7 is formed on the dielectric layer 5. The conductive layer 3 will be used to form the storage electrode, and the dielectric layer 5 preferably has a relatively high dielectric constant. The alumina layer will be patterned to provide an alumina mask for the conductive layer 3 and the dielectric layer 5. Accordingly, a patterned etching mask 9 is formed on the alumina layer 7, and this patterned etching mask 9 can be formed from photoresist or an oxide.
A dielectric layer formed from BST or PZT, however, may be susceptible to high-speed oxygen diffusion during oxidation steps such as an oxygen annealing step. This oxygen diffusion may result in the oxidation of the capacitor electrodes adjacent the dielectric layer during an oxidation step. Because electrode oxidation may reduce the electrical conductivity of the electrodes, an oxidation resistant and highly conductive material such as platinum (Pt), iridium dioxide (IrO.sub.2), or ruthenium dioxide (RuO.sub.2) is preferably used to form the storage electrode layer.
A storage electrode layer formed from platinum, iridium dioxide, or ruthenium dioxide, however, may be difficult to etch using a mask formed from oxide or photoresist. This difficulty may result because these materials have a low etching selectivity with respect to oxide and photoresist. Pattern formation and control may thus be difficult. Accordingly, etching mask layers formed from alumina have been used because a high degree of etching selectivity can be achieved when etching materials such as platinum, iridium dioxide, or ruthenium dioxide.
In FIG. 1B, portions of the alumina layer exposed by the patterned etching mask 9 are etched to form the patterned alumina layer 7a. After removing the patterned etching mask 9, the dielectric layer 5 and the conductive layer 3 are patterned by an etching step using the patterned alumina layer 7a as a mask. A plurality of capacitor structures are thus formed wherein each capacitor structure includes a conductive layer 3a and a dielectric layer 5a.
As discussed above, capacitor structures including a dielectric layer of BST or PZT, and a conductive layer of platinum, iridium dioxide, or ruthenium dioxide, can be patterned using a patterned alumina masking layer. This alumina layer, however, may have a relatively slow etching rate because the etching may be performed by sputtering only and not by chemical reaction. Accordingly, patterning related problems may develop.
Notwithstanding the above-mentioned methods, there continues to exist a need in the art for improved methods and systems for forming memory cell capacitors.